Various techniques for enhancing semiconductor device performance through manipulation of carrier mobility have been investigated in the semiconductor industry. One of the key elements in this class of technology is the manipulation of stress in the channel of transistor devices. Some of these methods utilize a carbon-substituted single crystal silicon (Si:C) layer within a silicon substrate to change the lattice constant of the silicon material in the channel. While both silicon and carbon have identical electronic outer shells and the same crystal structure, that is, “the diamond structure,” their room temperature lattice constants are different with values of 0.5431 nm and 0.357 nm, respectively. By substituting some of the silicon atoms in single crystal silicon with carbon atoms, a single crystal structure with a smaller lattice constant than that of pure silicon may be obtained.
To increase the amount of stress on adjoining semiconductor structures, it is necessary to increase the carbon content. In other words, the higher the carbon content in an Si:C layer, the higher the stress on adjoining structures. Incorporation of carbon into a silicon substrate during the manufacture of silicon substrates is very difficult due to the low equilibrium solubility of carbon (3.5×1017/cm3 or 7 ppm in atomic concentration) at the melting point of silicon. Practically, carbon cannot be incorporated into the silicon substrate during the growth of silicon ingot. However, a higher metastable solubility limit up to 7.0×1020/cm3 (1.4% in atomic concentration) was observed during the process of solid phase epitaxy of a carbon implanted silicon layer in bulk silicon wafers according to Strane et al., “Carbon incorporation into Si at high concentrations by ion implantation and solid phase epitaxy,” J. Appl. Phys. 79 (2), Jan. 1996, pp. 637-646. In the experiments described in Strane et al., the silicon substrates were first amorphized with a silicon implant and then implanted with carbon atoms. By performing solid phase epitaxy, a carbon-substituted single crystal silicon layer was regrown from the carbon implanted silicon layer. Strane et al., also established that after solid phase epitaxy, the carbon atoms occupy substitutional sites to form an Si:C layer. However, the presence of a band of defects corresponding to the end-of-range defects due to the silicon amorphization implant was also observed as well. Furthermore, at a high carbon concentration of 1.9%, a high level of crystalline defects was observed in the Si:C layer.
Since then, due to the potential benefit of enhancing performance of CMOS transistors, formation of Si:C layers by solid phase epitaxy has been investigated further despite the difficulties of obtaining low defect density Si:C layers. Formation of an Si:C layer with a high carbon concentration between 0.1% and 5%, preferably between 0.5% and 2.0% has been pursued due to the advantageous properties of generating a high level of stress. It has been found that the higher the carbon concentration in the Si:C layer is, the higher the defect density in the resulting Si:C layer. However, a high level of crystalline defect density is detrimental to the CMOS transistor performance since the defects serve as a leakage path for the off-current of the transistor. The defects in the strained single crystal layer also cause stress relief and deleteriously impact the mobility gains from the stress engineering.
A CMOS transistors may be built on a carbon-substituted single crystal silicon layer by utilizing relaxed Si:C layer as a substrate and growing epitaxial silicon on top of it. One method of obtaining an Si:C layer with a smaller lattice constant than that of silicon is to grow a thick Si:C layer with the thickness exceeding the critical thickness for the generation of crystalline defects. An alternative method is to grow an Si:C layer on a silicon-on-insulator (SOI) substrate so that the entire Si:C layer on top of the buried oxide layer has a smaller lattice constant than that of silicon. Silicon may be epitaxially grown on the relaxed Si:C layer so that the lattice constant of the silicon material matches that of the underlying relaxed Si:C. In this case, the epitaxially grown silicon is under a biaxial compressive stress in the plane of epitaxial growth. An N-type field effect transistor (NFET) built in such a substrate has enhanced electron mobility and consequently an increased on-current.
Alternatively, CMOS transistors may be built by embedding Si:C layers in the source and drain regions of a field effect transistor that is built on a silicon substrate. The presence of the embedded Si:C layers in the source and drain creates a uniaxial tensile stress in the channel region along the direction of the movement of carriers. Such stress enhances the mobility of electrons in the transistor. Consequently, an N-channel field effect transistor (NFET) built in such a substrate has enhanced mobility and consequently an enhanced on-current.
Therefore, there exists a need for a semiconductor structure and methods for fabricating a low defect, high carbon concentration Si:C layer.
There exists another need for a semiconductor structure and methods for locally incorporating a low defect, high carbon concentration Si:C layer epitaxially into a field effect transistor.